A manufacturing method and a layout for a monolithic hyperfrequency integrated circuit on a substrate (MMIC) is disclosed in patent specification U.S. Pat. No. 5,405,797 (Brugger). A Schottky diode and a HFET are manufactured in accordance with a semi-planar layout on the basis of a stack of layers composed of semiconducting materials. The object is to provide a simpler method of obtaining the layout. To achieve this, the method used in said document enables contact regions of the Schottky diode and of the HIFET to be manufactured simultaneously.
HFET is to be taken to mean a field effect transistor having a heterostructure. The above-described method of producing a layout comprises a first step of growing a first group S of epitaxial layers on a semi-insulating GaAs substrate. These layers S can suitably be used to manufacture the Schottky diode. The method further includes a step of manufacturing an etch-stop layer A comprising aluminium (Al). Said method further includes a step of photolithographically forming a mask covering the region of the Schottky diode, said mask having apertures delimiting the region of the HFET transistor. An ion implantation 0 is carried out through said apertures to form insulating wells around the diode region in the previously manufactured epitaxial layers. The method further includes a second step of growing a second group H of epitaxial layers throughout the surface of the stop layer, i.e. on the diode region as well as on the insulating wells surrounding it. The epitaxial layers H manufactured in this second growth step can suitably be used to generate the HFET transistor. The method further includes a second photolithographic step to form a mask which covers the transistor region and which includes apertures which delimit the diode region. Through said apertures, the layers H which are specific to the transistor and which are situated above diode layers S in the diode region are eliminated by etching down to the stop layer A. This results in a layout comprising the diode layers S surrounded by insulating wells, and comprising, laterally arranged on these insulating wells, the layers H which are specific to the HFET transistor and which are formed in relief with respect to the diode layers. As a result, the HFET transistor is laterally insulated from the diode by a mesa and vertically by a subjacent insulating well. Next, the photolithographic mask is eliminated and the contacts of the electrodes of the diode and the transistor are simultaneously formed.
In such a manufacturing method, it is necessary to form, prior to the first photolithographic step, a mask centering pattern in a region which is specifically reserved for the substrate. This preliminary stage in the manufacture of a centering pattern is very well known by those skilled in the art and is never described because it is necessarily used on a large scale in all techniques for manufacturing semiconductor devices by means of photolithographic steps. This step of manufacturing a centering pattern is both indispensable and non-pertinent because the centering pattern is not an integrated circuit element.
Consequently, this is a step which is costly in terms of means and the amount of time involved, because it employs a photolithographic mask specifically for forming the centering pattern, and it must be added to the other steps in the manufacture of integrated circuit elements.
In the known manufacturing method, a step of forming the centering pattern must necessarily be carried out by means of a first photolithographic step, followed, in succession, by a second photolithographic step, etching of superposed epitaxial layers, which are necessary to form the transistor and which cover the diode region, which photolithographic steps serve to remove all layers apart from the layers in the transistor region, thereby forming a mesa. This method has drawbacks. First, two successive photolithographic steps are necessary. Second, etching of a number of superposed layers results in a rather high mesa, which adversely affects the formation of conducting strips which are customarily formed to connect electrodes of the element insulated by the mesa to contact pads of other integrated circuit elements situated at a lower level. In the case of a fairly high mesa, the conducting strips are difficult to produce in a uniform thickness and they are liable to fracture when the slope changes.
In addition, a particular drawback resides in that etching of a number of superposed layers causes slope irregularities, referred to as undercutting, which is caused by the fact that the successive layers are composed of different materials having different etch rates, so that the upper layers successively overhang the subjacent layers which are etched one after the other. In this case, also the conducting strips formed on the slopes of the mesa are susceptible to fracture. Even if one of the connections is formed by a buried layer, as suggested in the cited document, the other connections must necessarily be made by means of conducting strips on the slope of the mesa, as a result of which they are fragile.
The known method not only requires a mask which is used specifically for centering, but also each subsequent mask used has a unique function in the formation of the layout.